The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. The 256Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. It is designed to operate in 3.3V memory systems.

Features

• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive edge of system clock
• Internal, pipelined operation; column address can be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge and auto refresh modes
• Self refresh mode (not available on AT devices)
• Auto refresh
• 64ms, 8192-cycle refresh (commercial and industrial)
• 16ms, 8192-cycle refresh (automotive)
• LVTTL-compatible inputs and outputs
• Single 3.3V ±0.3V power supply