Details
The 74AHC273D is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC273 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs, load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced LOW, independent of clock or data inputs, by a LOW on the MR input.
Features
- Balanced propagation delays
- All inputs have Schmitt-trigger actions
- Inputs accept voltages higher than VCC
- Ideal buffer for MOS microcontroller or memory
- Common clock and master reset
- Input levels:
- For 74AHC273: CMOS level
- ESD protection:
- HBM EIA/JESD22-A114E exceeds 2000 V
- MM EIA/JESD22-A115-A exceeds 200 V
- CDM EIA/JESD22-C101C exceeds 1000 V
- Multiple package options
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Zusatzinformation
| Hersteller | Nexperia |
|---|---|
| Herstellerteilenummer | 74AHC273D |
| Datenblatt | Download |
| Betriebsspannung | 2V - 5.5V |
| Anzahl der Flip-Flop | 8 |
| Betriebstemp. | -40°C - +125°C |
| Anzahl der Pins | 20 |
| Gehäuse | SOIC-20 |
| Montagetyp | SMD |
| Date Code | - |
| RoHS | RoHS-Konform |
| Qualifizierung | - |
| Lieferzeit | Am nächsten Arbeitstag |